1. Field of the Invention
This invention relates to a power semiconductor device, and more particularly to a power semiconductor device having a superjunction structure.
2. Background Art
The ON resistance of a power semiconductor device such as a vertical power MOSFET (metal oxide semiconductor field effect transistor) greatly depends on the electric resistance of its conduction layer (drift layer). The dopant concentration that determines the electric resistance of the drift layer cannot exceed a maximum limit, which depends on the breakdown voltage required for a pn junction between the base layer and the drift layer. Thus there is a tradeoff between the device breakdown voltage and the ON resistance. Improving this tradeoff is important for improving the performance of low power consumption devices. This tradeoff has a limit determined by the device material. Overcoming this limit is the way to realizing devices with low ON resistance beyond existing power devices.
As an example MOSFET overcoming this limit, a MOSFET having a structure called a superjunction structure is known, where p-pillar layers and n-pillar layers are alternately buried in the drift layer (see, e.g., JP-A 2004-282007 (Kokai)). In the superjunction structure, a non-doped layer is artificially produced by equalizing the amount of charge (amount of impurities) contained in the p-pillar layer with the amount of charge contained in the n-pillar layer. Thus, while holding high breakdown voltage, current is passed through the highly doped n-pillar layer. Hence low ON resistance beyond the material limit can be achieved.
Thus, in a vertical power MOSFET, the superjunction structure can be used to realize an ON resistance/breakdown voltage tradeoff beyond the material limit. By such an improved tradeoff, the chip area can be decreased with the ON resistance kept at a prescribed value. In this case, the chip area is decreased with the operating current kept constant, which results in increasing the density of current flowing in the chip. Hence the decrease in chip area also results in increasing current density during bipolar operation of the vertical power MOSFET, such as during avalanche breakdown and during recovery operation of the built-in diode. If the current density during bipolar operation increases, the carrier density in the device also increases. If the carrier density in the device increases by a certain degree or more, carrier charging results in increasing electric field strength and causing current concentration, and the device leads to breakdown. That is, another problem has arisen where the decrease of ON resistance and the reduction of chip area due to the superjunction structure lead to the increase of current density, causing the decrease of avalanche withstand capability and recovery withstand capability.